----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:02:59 02/20/2013 
-- Design Name: 
-- Module Name:    SpaceInvadersHW_Top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SpaceInvadersHW_Top is
port(
  
  clk : in std_logic;
    
  
  color : out std_logic_vector(2 downto 0);
  HS, VS : out std_logic
 
  
  );
end SpaceInvadersHW_Top;

architecture Behavioral of SpaceInvadersHW_Top is

--SIGNALS-----------------------------------------------------------------------
  
  signal rst : std_logic := '0';
  
  --TEMP
  signal pixel_out : std_logic;
  
  --VGA Signals
  signal pixel_x, pixel_y : std_logic_vector(9 downto 0);
  signal blank : std_logic := '1';
  signal pix_en : std_logic;
  signal q_reg, q_next : std_logic;

-- COMPONENTS-------------------------------------------------------------------
  component VGA_Ctrl 
   port(
  clk, rst : in std_logic;
  pix_en : in std_logic;
  HS, VS : out std_logic;
  pixel_x, pixel_y : out std_logic_vector(9 downto 0);
  last_column, last_row : out std_logic;
  blank : out std_logic
  );
end component;

begin

-- Free running Toggle flip-flop to skip one clock cycle
  process (clk, rst)
    begin
      if (rst = '1') then 
        q_reg <= '0';
        
      elsif (clk'event and clk = '1') then
      q_reg <= q_next;
    end if;
  end process;
  
  -- Next state logic for the TFF
  q_next <= not q_reg;
  
  -- output for the TFF
  
  pix_en <= q_reg;

    -- VGA Controller instanciation
    VGA_thing : VGA_Ctrl
    port map (
              clk => clk,
              rst => rst,
              pix_en => pix_en,
              HS => HS,
              VS => VS,
              pixel_x => pixel_x,
              pixel_y => pixel_y,
              blank => blank);
--begin testing code
  process (pixel_y)
  begin
  if (pixel_y > "0010000000") then
              pixel_out <= '0';
				  else
				  pixel_out <= '1';
	end if;
  end process;
  
  color <= "000" when blank = '1' else
		       "001" when pixel_out = '0' else
				  	"100";
--end testing code
end Behavioral;

